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FMS6407
Features
Triple Video Drivers with Selectable HD/Progressive/SD/Bypass Filters
Description
The FMS6407 offers comprehensive filtering for TV, set top box or DVD applications. This part consists of a triple 6th order filter with selectable 30MHz, 15MHz, or 8MHz cutoff frequencies. The filters may also be bypassed so that the bandwidth is limited only by the output amplifiers. A 2 to 1 multiplexer is provided on each filter channel. The triple filters are intended for YPbPr, RGB and YC-CV signals. The DC clamp levels are set according to the input mux selection and the CV_SEL control input. YPbPr sync tips are clamped to 250mV, 1.125V and 1.125V respectively while RGB sync tips are all clamped to 250mV. CV mode clamps Y and CV to 250mV while C is clamped to 1.l25V. Sync clamp timing can be derived from the Y or Green input channel or from the external SYNC_IN pin. All channels nominally accept AC coupled 1Vpp signals. Selectable 0dB or 6dB gain allows the outputs to drive 1Vpp or 2Vpp signals into AC or DC coupled terminated loads with a 1Vpp input. Input signals cannot exceed 1.5Vpp and outputs cannot exceed 2.5Vpp. The FMS6407 draws 525mW from a single 5.0V supply. * Three video anti-aliasing or reconstruction filters * 2:1 Mux inputs for YPbPr / RGB or YPbPr / YC-CV inputs * Supports D1, D2, D3 and D4 video D-connector (EIAJ CP-4120) * Selectable 8MHz/15MHz/30MHz 6th order filters plus bypass for SD (480i), Progressive (480p) and HD (1080i/ 720p) * AC-coupled inputs include DC restore /bias circuitry * All outputs can drive AC or DC coupled 75 loads and provide either 0dB or 6dB of gain * 0.26% differential gain, 0.11 differential phase * Lead-free packaging
Applications
* Progressive scan * Cable set top boxes * Satellite set top boxes * DVD players * HDTV * Personal Video Recorders (PVR) * Video On Demand (VOD)
Functional Block Diagram
SYNC_IN YIN GIN / YIN EXT_SYNC 8MHz, 15MHz, 30MHz, Bypass Sync Strip YOUT / GOUT / YOUT
gM
250mV
PbIN BIN / CIN CV_SEL Clamp Control 8MHz, 15MHz, 30MHz, Bypass
PbOUT / BOUT/ COUT
gM
1.125V 250mV PrIN RIN / CVIN RGB 8MHz, 15MHz, 30MHz, Bypass 1.125V 250mV
Selectable 0dB or 6dB output gain PrOUT / ROUT/ CVOUT
gM
FSEL0 FSEL1
0dB
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DATA SHEET
FMS6407
DC Electrical Specifications
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted) Symbol ICC Vi Vil Vih VCLAMP1 VCLAMP2 PSRR Parameter Supply Current1 Input Voltage Max Digital Input Low1 Digital Input High1 Output Clamp Voltage Output Clamp Voltage Power Supply Rejection Ratio FSEL1, FSEL2, RGB, 0dB, EXT_SYNC, CV_SEL, SYNC_IN FSEL1, FSEL2, RGB, 0dB, EXT_SYNC, CV_SEL, SYNC_IN R,G,B,Y,CV Pb,Pr,C DC (all channels) 0 2.4 250 1.125 -40 Conditions VCC no load Min Typ 105 1.5 0.8 VCC Max Units 130 mA Vpp V V mV V dB
Standard Definition Electrical Specifications
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted) Symbol AVSD AVSD f1dBSD fCSD fSBSD dG d THD XTALK
INMUXISO
Parameter SD Gain, 0dB = `0'1
1 1
Conditions All Channels SD Mode All Channels SD Mode All Channels All Channels
1
Min 5.6 -0.4 5.5 40
Typ 6.0 0 6.75 8.2 56 0.26 0.11 0.4 -65 -70 73 80 10 4
Max Units 6.4 0.4 dB dB MHz MHz dB % % dB dB dB ns ns s
SD Gain, 0dB = `1'
-1dB Bandwidth for SD
-3dB Bandwidth for SD Attenuation: SD (Stopband Reject) Differential Gain Differential Phase Output Distortion (All Channels) Crosstalk (Channel-to-Channel) INMUX Isolation Signal-to-Noise Ratio Propagation Delay for SD SYNC to SYNC_IN Delay SYNC_IN Min Pulse Width
All Channels at f = 27MHz All Channels All Channels Vout = 1.8Vpp at 1MHz at 1.0MHz at 1.0MHz All Channels, NTC-7 Weighting, 4.2MHz lowpass, 100kHz Highpass
Delay from Input to Output at 4.5MHz
SNR tpdSD T1 T2
Progressive Scan (PS) Electrical Specifications
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted) Symbol AVPS AVPS f1dBPS Parameter PS Gain, 0dB = `0'
1 1 1
Conditions All Channels PS Mode All Channels PS Mode All Channels
Min 5.6 -0.4 10
Typ 6.0 0 13.5
Max Units 6.4 0.4 dB dB MHz
PS Gain, 0dB = `1'
-1dB Bandwidth for PS
Note: 1. 100% tested at 25C.
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Progressive Scan (PS) Electrical Specifications (Continued)
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted) Symbol fCPS fSBPS tpdPS T1 T2 Parameter -3dB Bandwidth for PS Attenuation: PS (Stopband Propagation Delay for PS SYNC to SYNC_IN Delay SYNC_IN Min Pulse Width Reject)1 Conditions All Channels All Channels at f = 54MHz
Delay from Input to Output at 10MHz
Min 40
Typ 15 48 45 10 2
Max Units MHz dB ns ns s
High Definition Electrical Specifications
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 1, gain = 6dB, RSOURCE = 37.5, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted) Symbol AVHD AVHD f1dBHD fCHD fSBHD tpdHD T1 T2 Parameter HD Gain, 0dB = `0' HD Gain, 0dB = `1'
1 1
Conditions All Channels HD Mode All Channels HD Mode HD1 Reject)1 All Channels All Channels All Channels at f = 74.25MHz
Delay from Input to Output at 20MHz
Min 5.6 -0.4 20 30
Typ 6.0 0 28 32 40 26 10 1.5
Max Units 6.4 0.4 dB dB MHz MHz dB ns ns s
-1dB Bandwidth for
-3dB Bandwidth for HD Attenuation: HD (Stopband Propagation Delay for HD SYNC to SYNC_IN Delay SYNC_IN Min Pulse Width
Bypass (Wide Bandwidth) Electrical Specifications
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 1, gain = 6dB, RSOURCE = 37.5, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted) Symbol AVWB AVWB f1dBWB fCWB tpdWB Parameter WB Gain, 0dB = WB Gain, 0dB = `0'1 `1'1 Conditions All Channels WB Mode All Channels WB Mode All Channels All Channels
Delay from Input to Output at 20MHz
Min 5.6 -0.4
Typ 6.0 0 50 80 10
Max Units 6.4 0.4 dB dB MHz MHz ns
-1dB Bandwidth for WB -3dB Bandwidth for WB Propagation Delay for WB
Note: 1. 100% tested at 25C.
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DATA SHEET
FMS6407
Absolute Maximum Ratings (beyond which the device may be damaged)
Parameter DC Supply Voltage Analog and Digital I/O Output Current, Any One Channel (Do not exceed) Min -0.3 -0.3 Max 6 VCC + 0.3 60 Units V V mA
Note: Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded.
Reliability Information
Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Thermal Resistance (JA), TSSOP-20 Thermal Resistance (JA), ePAD TSSOP-20
Note: Package thermal resistance (JA), JEDEC standard multi-layer test boards, still air.
Min -65
Typ
Max 150 150 300
Units C C C C/W C/W
74 37.6
Recommended Operating Conditions
Parameter Operating Temperature Range VCC Range Input Source Resistance (RSOURCE) Min 0 4.75 5.0 Typ Max 70 5.25 150 Units C V
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Standard Definition Typical Performance Characteristics
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted)
SD Frequency Response
10 0
12
SD Group Delay vs. Frequency
60 40
1
Gain (10dB/div)
-10 -20 -30
Mkr Frequency Gain 6dB -1dB BW -3dB BW -53.82dB 3
Delay (ns)
20 0 -20 -40
1 = 8.2MHz (38.13ns)
-40 -50 -60 -70
Ref 400kHz 1 2 3 7.65MHz 8.54MHz 27MHz
fSBSD = Gain(ref) - Gain(3) = 59.82dB
-60 5 10 15 20 25 30 400kHz 5 10 15 20 25 30
400kHz
Frequency (MHz) SD Noise vs. Frequency
-50 -60 -70 0.1
Frequency (MHz) SD Differential Gain
NTSC
Differential Gain (%)
0 -0.1 -0.2 -0.3
Noise (dB)
-80 -90 -100 -110 -120 0 1.0 2.0 3.0 4.0 5.0 6.0
Min = -0.26 Max = 0.00 ppMax = 0.26
-0.4 1st 2nd 3rd 4th 5th 6th
Frequency (MHz)
SD Differential Phase
0.12
NTSC
Differential Phase (deg)
0.08
0.04
0.00
Min = -0.00 Max = 0.11 ppMax = 0.11
-0.04 1st 2nd 3rd 4th 5th 6th
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FMS6407
Progressive Scan Typical Performance Characteristics
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted)
PS Frequency Response
10 0
12
PS Group Delay vs. Frequency
30 20
Delay (10ns/div)
Gain (10dB/div)
-10 -20 -30 -40 -50 -60 -70 400kHz 10 20 30 40 50 60
Mkr Frequency Ref 400kHz 1 2 3 15.02MHz 16.67MHz 54MHz Gain 6dB -1dB BW -3dB BW -56.37dB 3
1
10 0 -10 -20
1 = 15MHz (20.32ns)
fSBPS = Gain(ref) - Gain(3) = 62.37dB
-30 400kHz 10 20 30 40 50
Frequency (MHz)
Frequency (MHz)
High Definition Typical Performance Characteristics
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 1, gain = 6dB, RS = 37.5, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted)
HD Frequency Response
10 0
1 2
HD Group Delay vs. Frequency
15 10
Gain (10dB/div)
-10 -20 -30 -40 -50
Mkr Ref 1 2 3 Frequency 400kHz 29.52MHz 33.10MHz 74.25MHz Gain 6dB -1dB BW -3dB BW -35.36dB
Delay (5ns/div)
5 0 -5 -10 -15
1
3
fSBHD = Gain(ref) - Gain(3) = 41.36dB
1 = 32MHz (8.60ns)
-60 400kHz 10
-20 20 30 40 50 60 70 80 90 400kHz 10 20 30 40 50 60 70 80 90
Frequency (MHz)
Frequency (MHz)
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Bypass (Wide Bandwidth) Typical Performance Characteristics
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 1, gain = 6dB, RSOURCE = 37.5, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz; unless otherwise noted)
WB Frequency Response
6.5 6.0 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4
2
WB Group Delay vs. Frequency
5.0 4.5 4.0 3.5 3.0 2.5
Mkr Frequency Ref 400kHz 1 2 60.16MHz 87.55MHz Gain 6dB -1dB BW -3dB BW 1
Delay (0.2ns/div)
Gain (0.5dB/div)
5.5
1
-0.6 -0.8 90
1 = 80MHz (0.29ns)
2.0 400kHz 10
20
30
40
50
60
70
80
400kHz 10
20
30
40
50
60
70
80
90 100
Frequency (MHz)
Frequency (MHz)
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DATA SHEET
FMS6407
Pin Configuration
Pin#
EXT_SYNC CV_SEL YIN
Pin
EXT_SYNC
Type Input
Description Selects the external SYNC_IN signal when set to logic `1', do not float Selects CV mode when set to logic `1' (sets C clamp to 1.125V and CV clamp to 250mV), do not float Y (Luminance) input may be connected to a signal which includes sync Green or Y input Pb input Blue or C (Chrominance) input Pr input Red or CV (Composite Video) input Selects filter corner frequency or bypass, see table, do not float Selects filter corner frequency or bypass, see table, do not float Must be tied to Ground, do not float Must be tied to Ground, do not float Selects output gain of 0dB when set to logic `1', do not float Pr, Red, or CV output Pb, Blue, or C output Y, Green, or Y output Selects RGB MUX inputs and clamp mode when set to logic `1', do not float External sync input signal, square wave crossing Vil and Vih input thresholds, do not float +5V supply, do not float +5V supply, do not float
1 2 3 4 5 6 7 8 9 10
20
VCC VCC SYNC_IN RGB
1
GIN/Y PbIN BIN/C PrIN RIN/CV FSEL0 FSEL1
FMS6407 20-pin TSSOP or ePAD TSSOP
19 18 17 16 15 14 13 12 11
2
CV_SEL
Input
YOUT PbOUT PrOUT 0dB GND GND
3
YIN
Input
4 5 6 7 8 9 10 11 12 13 14 15 16 17
GIN PbIN BIN PrIN RIN FSEL0 FSEL1 GND GND 0dB PrOUT PbOUT YOUT RGB
Input Input Input Input Input Input Input Input Input Input Output Output Output Input
18
SYNC_IN
Input
19 20
VCC VCC
Input Input
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Gain Settings
0dB, Pin 13 0 1
above ground.
Sync Settings
VIN* 1Vpp 1Vpp VOUT* 2Vpp 1Vpp EXT_SYNC, Pin1 0 1 Sync Source
Y/G input, Pin 3/4 6
Gain (dB) 0
SYNC_IN input, Pin 2
* Video level, does not include clamp voltage which will offset the input
Filter Settings
FSEL1, Pin 10 0 0 1 1 FSEL0, Pin 9
0
Filter -3dB Freq 8.2MHz 15MHz 32MHz Filter Bypass
Video Format SD, 480i PS, 480p HD, 1080i, 720p -
Sync Format Bi-level, 4.7s pulse width Bi-level, 2.35s pulse width Tri-level, 589ns pulse width Bi-level, 2.35s pulse width
1
0
1
I/O and Clamp Settings
RGB, Pin 17 0 CV_SEL, Pin 2
X (don't care)
Input Y, Pin 3 Pb, Pin 5 Pr, Pin 7 G/Y, Pin 4 B/C, Pin 6 R/CV, Pin 8
Output Y, Pin 16 Pb, Pin 15 Pr, Pin 14 G, Pin 16 B, Pin 15 R, Pin 14 Y, Pin 16 C, Pin 15 CV, Pin 14
Clamp Voltage 250mV 1.125V 1.125V 250mV 250mV 250mV 250mV 1.125V 250mV
1
0
1
1
Y/G, Pin 4 C/B, Pin 6 CV/R, Pin 8
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DATA SHEET
FMS6407
Functional Description
Introduction
The FMS6407 is a next generation filter solution from Fairchild Semiconductor addressing the expanding filtering needs for televisions, set top boxes, and DVD players including progressive scan capability. The product provides selectable filtering with cutoff frequencies of 30MHz, 15MHz, and 8.0MHz on the YPbPr, RGB and YC-CV channels. In addition, the filters can be bypassed for wider bandwidth applications. The FMS6407 allows consumer devices to support a variety of resolution standards with the same hardware. Multiplexers on the YPbPr / RGB / YC-CV channels provide further flexibility. When the input multiplexer is changed from YPbPr to RGB mode the sync tip clamp voltages are changed appropriately. All three channels are set for 250mV sync tips to reduce DC-coupled power dissipation for RGB inputs. The lower output bias voltage is not suitable for the PbPr outputs so for YPbPr inputs these signals are clamped to 1.125V while Y is still clamped to 250mV. For systems running YPbPr and YC-CV signals, the Y and CV signals will be clamped to 250mV while C is clamped to 1.125V. Sync tip clamping voltages are set by forcing the desired DC bias level during the active sync period. For systems without sync on green, an external sync input is provided. If sync exists on the Y input signal but not on the G input signal, the RGB and EXT_SYNC control inputs may be wired together on the PCB to switch the sync source with the input source. Both standard definition (bi-level) and high definition (trilevel) sync are supported at YIN and SYNC_IN depending on the FSEL[1:0] inputs. Standard definition (480i) and progressive (480p) signals are clamped by forcing the signal to the desired voltage during the sync pulse. For signals with sync, the sync tip itself will be forced to the clamp voltage (typically 250mV). When high definition sync is present (tri-level sync) the sync tip duration is too short to allow this approach. In order to accurately clamp HD signals, the sync pulse starts a timer and the actual clamping is done at the blanking level right after the sync pulse. The sync tip will still typically be placed at 250mV. All three outputs are driven by amplifiers with selectable gains of 0dB or +6dB. These amplifiers can drive two terminated video loads (75) to 2Vpp with a 1Vpp input when set to 6dB gain. The input range is limited to 1.5Vpp and the output range is limited to 2.5Vpp. All control inputs must be tied to VSS or VCC. Do not leave them floating.
not include sync, the FMS6407 can be used in External SYNC Mode. When the FMS6407 is used in external sync mode, (EXT_SYNC pin is high), a pulsed input must be applied to the SYNC_IN pin. If there is no video signal present, therefore no sync signal present, there must still be an input applied to the SYNC_IN pin. When there is no video signal on the video inputs SYNC_IN can be a sync pulse every 60s to mimic the slowest sync in a regular video signal. The following two sections discuss the sync processing and timing required in more detail.
SD and Progressive Scan Video Sync Processing
The FMS6407 must control the DC offset of AC-coupled input signals since the average DC level of video varies with image content. If the input offset is allowed to wander, the common mode input range of the amplifiers can be exceeded leading to signal distortion. DC offset adjustment is referred to as clamping or in some cases, biasing, and must be done at the correct time during each video line. The optimum time is during the sync pulse since it is the lowest input voltage. This approach works well for 480i and 480p signals since the sync tip duration is long enough to allow the DC-offset errors to be compensated from line to line. The DC-offset of the sync tip is adjusted as illustrated in Figure 1 by forcing a current on the input during the sync pulse. The sync tip will be clamped to approximately 250mV. Signals like Pb and Pr with a symmetric voltage range (350mV) will be clamped to approximately 1.125V. Note that the following diagrams indicate output voltage levels for both 0dB and 6dB gain (1Vpp and 2Vpp video signals at the FMS6407 output pin).
0dB Gain 6dB
1475mV 1875mV 1125mV 1125mV 775mV 425mV Required Pb Offset
1250mV 2250mV
Av = 1 (0dB) or 2 (6dB)
Av*700mV
550mV 250mV 0mV 850mV 250mV 0mV
Active Active Video
Av*300mV
Required Sync Tip Offset
Figure 1. Bi-Level Sync Tip Clamping and Bias In some cases, the sync voltage may be compressed to less than the nominal 300mV value. The FMS6407 can successfully recover SD and Progressive Scan sync which is greater than 100mV (compressed to 33% of nominal). The FMS6407 can properly recover sync timing from luma and green which include sync. If none of the video signals includes sync, the EXT_SYNC control input can be set high
External Sync Mode
The FMS6407 can properly recover sync timing from video signals that include sync. If the Y-input video signals does
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DATA SHEET
and an external sync signal must be input on the SYNC_IN pin. Refer to the External Sync section for more details. The timing required for this operating mode is shown in Figure 2.
0dB Gain 6dB 950mV 1650mV Av = 1 (0dB) or 2 (6dB)
Sync Timing
Normally, the FMS6407 will respond to bi-level sync and clamp the sync tip during period `B' in Figure 4(a). When the filters are switched to high definition mode (30MHz) the sync processing will respond to tri-level sync and clamp to the blanking level during period `C' in Figure 4(b).
(a)
2250mV
Av*700mV 250mV 0mV 250mV 0mV
Active Video
Required Blanking Offset
480i and 480p
850mV
T1 T2
True Sync Position
Allowable SYNC_IN
250mV A B C
Figure 2. Bi-Level External Sync Clamping and Bias
(b)
2250mV
HD Video Sync Processing
When the input signal is a high definition signal, the tri-level sync pulse is too short to allow proper clamp operation. Rather than clamp during the sync pulse, the sync pulse is located and the signal is clamped to the blanking level. This is done in such a way that the sync tip will still be set to approximately 250mV. The EXT_SYNC control input selects the sync stripper output or the SYNC_IN pin for use by the clamp circuit. This means that the SYNC_IN timing for HD signals is different than the timing for SD or PS signals. For HD signals, the SYNC_IN signal must be high when the clamp must be active. This is during the time immediately after the sync pulse while the signal is at the blanking level. This operation is shown in Figure 3. Note that the following diagrams indicate output voltage levels for both 0dB and 6dB gain (1Vpp and 2Vpp video signals at the FMS6407 output pin).
0dB Gain 6dB 1250mV 2250mV Av = 1 (0dB) or 2 (6dB)
720p and 1080i
1450mV 850mV 250mV A B
B
C
Figure 4. Sync Timing; Bi-Level (a), Tri-Level (b) The tri-level sync pulse is located such that the broad pulses in the vertical interval do not trigger the clamp. In order to improve the system settling at turn-on, the broad pulses will be clamped to just above ground. Once the broad pulses (and tri-level sync tips) are above ground, the normal clamping process takes over and clamps to the blanking level during period `C' in Figure 4(b). The FMS6407 is designed to support the video standards and associated sync timings shown in Table I on page 12 (additional standards such as 483p59.94 will also work correctly). The filter settings table from page 9 is repeated on page 12 for convenience.
850mV 1450mV 550mV 250mV 0mV 850mV 250mV 0mV
True Sync Position
0H
Av*700mV
Active Video
Av*300mV
Av*300mV
Required Sync Tip Offset (Next Sync Tip Will Be Offset Correctly)
T1 Allowable SYNC_IN
T2
Figure 3. Tri-Level Blanking Clamp NOTE: Tri-level sync may only be compressed 5%. If tri-level sync is compressed more than 5% it may not be properly located.
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FMS6407
Filter Settings
FSEL1, Pin 10 0 0 1 1 Table I Format 480i 480p 720p 1080i Refresh
30Hz 60Hz 60Hz 30Hz
FSEL0, Pin 9
0
Filter -3dB Freq 8.2MHz 15MHz 32MHz Filter Bypass
Video Format SD, 480i PS, 480p HD, 1080i, 720p -
Sync Format Bi-level, 4.7s pulse width Bi-level, 2.35s pulse width Tri-level, 589ns pulse width Bi-level, 2.35s pulse width
1
0
1
Sample Rate 13.5MHz 27MHz 74.25MHz 74.25MHz
Period (T) 74ns 37ns 13.4ns 13.4ns
A 20T = 1.5s 20T = 750ns 70T = 938ns 44T = 589ns
B 64T = 4.7s 64T = 2.35s 40T = 536ns 44T = 589ns
C 61T = 4.5s 61T = 2.25s 220T = 2.95s 148T = 1.98s
H-Rate 15.75kHz 31.5kHz 45kHz 33.75kHz
Note: Timing values are approximate for 30Hz/60Hz refresh rates.
Application Information
Input Circuitry
The DC restore circuit in the FMS6407 requires a source impedance (Rsource = Rs || RT) of less than or equal to 150 for correct operation. Driving the FMS6407 with a highimpedance source (e.g. a DAC loaded with 330) will not yield optimum results.
for proper operation. Clamping a CV signal to 1.125V will result in clipping the top of the signal and clamping a Pr signal to 250mV will result in clipping the bottom of the signal. The 220F capacitor coupled with the 150 termination, as shown in the Typical Application Circuit of Figure 5, forms a high pass filter that blocks the DC while passing the video frequencies and avoiding tilt. Any value lower than 220F will create problems, such as video tilt. Higher values, such as 470F - 1000F are the most optimal output coupling capacitor. By AC coupling, the average DC level is zero. Thus, the output voltages of all channels will be centered around zero.
Output Drive
The FMS6407 is specified to operate with output currents typically less than 60mA, more than sufficient for a dual (75) video load. Internal amplifiers are current limited to approximately 100mA and should withstand brief duration short circuit conditions, however this capability is not guaranteed. The maximum specified input voltage of 1.5Vpp can be sustained for all inputs. When the input is clamped to 1.125V, this does not result in a meaningful output signal. With a gain of 6dB, the output should be 1.125V 1.5V which is not possible since the output cannot drive below ground. This condition will not damage the part; however, the output will be clipped. For signals which are clamped to 250mV, this does not occur. Signals that are at midscale during SYNC (Pb, Pr, C) must be clamped to 1.125V and signals that are at their lowest during SYNC (Y, CV, R, G, B) must be clamped to 250mV
Sync Recovery
The FMS6407 will typically recover bi-level sync with amplitude greater than 100mV (33% compressed relative to the nominal 300mV amplitude). The FMS6407 looks for the lowest signal voltage and clamps this to approximately 250mV at the output. Tri-level sync may not be compressed more than 5% (15mV) for correct operation. Tri-level sync is located by finding the edges of the tri-level pulse and running a timer to operate the clamp during the back porch interval. Since only the Y/G channel is processed for sync recovery, Y and CV inputs must be synchronous.
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Power Dissipation
The FMS6407 output drive configuration must be considered when calculating overall power dissipation. Care must be taken not to exceed the maximum die junction temperature. The following example can be used to calculate the FMS4607's power dissipation and internal temperature rise. Tj = TA + Pd * JA where Pd = PCH1 + PCH2 + PCH3 and PCHx = Vs * ICH where VO = 2Vin + 0.280V ICH = (ICC / 3) + (VO/RL) Vin = RMS value of input signal ICC = 105mA Vs = 5V RL = channel load resistance Board layout can also affect thermal characteristics. Refer to the Layout Considerations Section for more information. The FMS6407 is specified to operate with output currents typically less than 60mA, more than sufficient for a single (150) video load. Internal amplifiers are current limited to a maximum of 100mA and should withstand brief duration short circuit conditions, however this capability is not guaranteed. (VO2/RL)
* * * * *
Include 10F and 0.1F ceramic bypass capacitors Place the 10F capacitor within 0.75 inches of the power pin Place the 0.1F capacitor within 0.1 inches of the power pin Connect all external ground pins as tightly as possible, preferably with a large ground plane under the package Layout channel connections to reduce mutual trace inductance Minimize all trace lengths to reduce series inductances. If routing across a board, place device such that longer traces are at the inputs rather than the outputs.
*
If using multiple, low impedance DC coupled outputs, special layout techniques may be employed to help dissipate heat. For dual-layer boards, place a 0.5" to 1" (1.27cm to 2.54cm) square ground plane directly under the device and on the bottom side of the board. Use multiple vias to connect the ground planes. For multi-layer boards, additional planes (connected with vias) can be used for additional thermal improvements. Worse case additional die power due to DC loading can be estimated at (VCC2/4Rload) per output channel. This assumes a constant DC output voltage of VCC2. For 5V VCC with a dual DC video load, add 25/(4*75) = 83mW, per channel. A package option with an exposed DAP is available for improved thermal performance, see Ordering Information on page 16. For layout recommendations using the ePAD package , refer to the following: http://www.amkor.com/products/ notes_papers/epad.pdf
Layout Considerations
General layout and supply bypassing play major roles in high frequency performance and thermal characteristics. Fairchild offers a demonstration board, FMS6407DEMO, to use as a guide for layout and to aid in device testing and characterization. The FMS6407DEMO is a 4-layer board with a full power and ground plane. For optimum results, follow the steps below as a basis for high frequency layout:
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DATA SHEET
FMS6407
YIN
Rs 75 RT 75 Rs 75 RT 75 Rs 75 RT 75 Rs 75 RT 75 Rs 75 RT 75 Rs 75 RT 75
0.1F
VCC
3
20 19
+5V 0.1F 1F
YIN
VCC
Rsource = RS || RT 0.1F 4
FMS6407 20L TSSOP
GIN/Y YOUT
16 75
May also be DC coupled
GIN/Y
220F
75 Video Cables
75 0.1F
PbIN
5
PbIN PbOUT
15 75
220F
75 Video Cables
75 0.1F 6
BIN/C
BIN/C
PrOUT
14 75
220F
75 Video Cables
75 0.1F
PrIN
7
PrIN
0.1F
RIN/CV
8
GND RIN/CV GND
Note: Pins 1, 2, 9, 10, 13, 17, and 18 will need to be set according to the input signal format
12
11
Figure 5. Typical Application Circuit
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FMS6407
DATA SHEET
Package Dimensions
TSSOP-20 and ePAD TSSOP-20
4 B 1.00 1.00 DIA. 321 B B C
E/2 1.00 E E1 5 C L
0.20 2X N/2 TIPS
C
A-B
D
N
7 D 4 SEE DETAIL "A"
X
e/2 X X = A AND B X = A AND B
A
4
TOP VIEW
END VIEW
EVEN LEAD SIDES TOPVIEW
ODD LEAD SIDES TOPVIEW
(14)
b
bbb M C A-B A2
D
9
SIDE VIEW
(b) A C WITH PLATING aaa C 8 0.25 c1 (c) b1
0.05 C
H
3 e D 5 A1 SEATING PLANE
PARTING LINE H
13
P
L6 BASE METAL (OC) (1.00)
SECTION "B-B"
SCALE: 120/1 (SEE NOTE 10) (14)
DETAIL "A"
P1 13 SCALE: 30/1 (VIEW ROTATED 90 C.W.)
SYM
Common Dimensions
MIN. NOM. MAX. 1.10 0.05 0.85 0.19 0.19 0.09 0.09 6.40 4.30 0.22 0.10 0.127 6.50 4.40 0.65 BSC 6.40 BSC 0.50 0.60 20 4.2 3.0 0 8 0.70 6 7 13 13 0.20 0.16 6.60 4.50 0.90 0.076 0.30 0.25 9 0.15 0.95 Note
NOTES:
1. 2. 3. 4. DIE THICKNESS ALLOWABLE IS 0.2790.0127 (.0110.0005 INCHES) DIMENSIONING & TOLERANCES PER ASME. Y14.5M-1994. DATUM PLANE H LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. DATUM A-B AND D TO BE DETERMINED WHERE CENTERLINE BETWEEN LEADS EXITS PLASTIC BODY AT DATUM PLANE H. 5. "D" & "E1" ARE REFERENCE DATUM AND DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, AND ARE MEASURED AT THE BOTTOM PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm ON D AND 0.25mm ON E PER SIDE. DIMENSION IS THE LENGTH OF TERMINAL FOR SOLDERING TO A SUBSTRATE. TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.076mm AT SEATING PLANE. THE LEAD WIDTH DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.07mm TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND AN ADJACENT LEAD SHOULD BE 0.07mm FOR 0.65MM PITCH, 0.08MM FOR 0.50MM PITCH AND 0.07MM FOR 0.40MM PITCH PACKAGES. SEE SECTION "B-B". SECTION "B-B" TO BE DETERMINED AT 0.10 TO 0.25 MM FROM THE LEAD TIP. CONTROLLING DIMENSION: MILLIMETERS. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153 VARIATIONS AA/AAT, AB-1/ABT-1, AB/ABT, AC/ACT, AD/ADT, AE/AET BC-1/BCT-1, BD-1/BDT-1, BE/BET, CA/CAT & CD/CDT AND MO-194 VARIATIONS AC/ACT & AF/AFT. DIMENSIONS "P" AND "P1" ARE THERMALLY ENHANCED VARIATIONS. VALUES SHOWN ARE MAXIMUM SIZE OF EXPOSED PAD WITHIN LEAD COUNT AND BODY SIZE. END USER SHOULD VERIFY AVAILABLE SIZE OF EXPOSED PAD FOR SPECIFIC DEVICE APPLICATION.
EXPOSED PAD VIEW
A A1 A2 aaa b b1 bbb c c1 D E1 e E L N P P1 OC
5 5
6. 7. 8. 9.
Note: For 0.65mm pitch. All dimensions in millimeters.
10. 11. 12.
13.
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DATA SHEET
FMS6407
Ordering Information
Model FMS6407 FMS6407 FMS6407 FMS6407 Part Number FMS6407MTC20 FMS6407MTC20X FMS6407MTF20 FMS6407MTF20X Lead Free Yes Yes Yes Yes Package TSSOP-20 TSSOP-20 ePAD TSSOP-20 ePAD TSSOP-20 Container Tube Tape and Reel Tube Tape and Reel Pack Qty 94 2500 94 2500
Temperature range for all parts: 0C to +70C.
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FMS6407
DATA SHEET
www.fairchildsemi.com
(c) 2005 Fairchild Semiconductor Corporation

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